1. Field of the Invention
A structure and a method of manufacturing a liquid crystal display (LCD) device uses a thin film transistor (TFT) as a switching element. More specifically, structure and a method for manufacturing an LCD in which an increase in contact resistivity of a surface of a metal layer is prevented such that distortion in electrical characteristics caused by such an increased contact resistivity is prevented.
2. Description of the Background Art
Generally, a substrate of a conventional LCD includes a plurality of a gate bus lines 60 and a plurality of data bus lines 70, which are arranged to cross each other and are perpendicular to each other as shown in FIG. 1. In an area surrounding adjacent ones of the gate bus lines 60 and the data bus lines 70, a pixel electrode 80 is disposed. At the intersection portion of the gate bus line 60 and the data bus line 70, a TFT 37 which is connected to the pixel electrode 80 is provided.
The TFT 37 includes a gate electrode 61 which is derived from the gate bus line 60, a source electrode 71 which is derived from the data bus line 70, a drain electrode 72 which faces the source electrode 71 and a semiconductor layer 90 which is located between the source electrode 71 and the drain electrode 72.
According to FIG. 1, the pixel electrode 80 has a portion which overlaps with some portions of the gate bus line 60. This overlapping portion of the pixel electrode 80 is a storage capacitor 33 for supporting a voltage which leaks from the pixel electrode 80 through the TFT 37.
Referring to the FIG. 2 (a cross sectional view of the FIG. 1 which is cut along the line IIxe2x80x94II), a conventional method of manufacturing the LCD shown in FIG. 1 is explained.
A chromium layer is deposited on a transparent glass substrate 10. After a photoresist is coated on the chromium layer, the chromium layer is patterned by exposing and developing using a mask. The chromium layer is etched by an etchant such as a CAN (Ceric Ammonium Nitrate) to form a gate bus line 60 and a gate electrode 61 which is derived from the gate bus line 60. After that, the remaining photoresist on the patterned chromium layer is removed by an organic solution such as NMP (N-Methyl-Pyrrolidone).
On the substrate which has the gate material (the gate bus line 60 and the gate electrode 61), a gate insulating layer 50 which includes an inorganic material such as SiNx or SiOx, an intrinsic amorphous silicon and an n+ type impurity doped amorphous silicon are sequentially deposited. A photoresist is then coated on the doped amorphous silicon. After patterning the photoresist by using a mask, the doped amorphous silicon and the intrinsic amorphous silicon are etched to form a semiconductor layer 90 and an ohmic contact layer 100 over the gate electrode 61.
On the entire surface of the substrate 10 which includes the ohmic contact layer 100, a chromium layer is deposited via a sputtering method. After a photoresist is coated on the chromium layer, the photoresist is patterned by exposing and developing using a mask. The chromium layer is etched by an etchant such as a CAN (Ceric Ammonium Nitrate) to form a data bus line 70 on the gate insulating layer 50. At the same time, a source electrode 71 which is derived from the data bus line 70 and a drain electrode 72 which faces the source electrode 71 are formed on the ohmic contact layer 100.
Exposed portions of the ohmic contact layer 100 between the source electrode 71 and the drain electrode 72 are fully removed via a dry etching method. The remaining photoresist on the source materials (the data bus line 70, the source electrode 71 and the drain electrode 72) are removed by an organic solution such as NMP (N-Methyl-Pyrrolidone).
On the substrate having the source materials, a passivation layer 55 is formed by depositing and/or coating SiNx, SiOx or BCB (Benzocyclobutene) which includes Si functional groups. A photoresist is coated on the passivation layer 55 and patterned by exposing and developing using a mask. By using a dry etching method, the passivation layer 55 is patterned by an etching gas including SF6/O2 gas or CF4/O2 gas. After that, a contact hole 30 exposing some portions of the drain electrode 72 is formed.
The detailed mechanism of forming the contact hole 30 is explained hereafter. The Si functional group of the passivation layer 55, especially, the portion of the passivation layer 55 which is exposed through the opening pattern of the mask reacts with the F radical of the etching gas so that the exposed portion of the passivation layer 55 is removed by converting the passivation layer material t o a volatile material such as a SiF4. At the same time, the photoresist is removed by ashing with O2 of the etching gas.
On the passivation layer 55 which has the contact hole 30, an ITO (Indium Tin Oxide) layer is deposited. After a photoresist is coated on the ITO layer, the photoresist is patterned by exposing and developing using a mask. The ITO layer is etched by an etchant such as a HCI to form a pixel electrode 80 which is connected to the drain electrode 72 through the contact hole 30.
A gate pad disposed at the end of the gate bus line 60 and a data pad disposed at the end of the data bus line 70 are shown in FIG. 3 which is a cross sectional view. Pads 92 are connected to the output of the driving IC with a TAB (Tape Automated Bonding). The pad 92 is formed when the bus lines (gate bus line 60 and data bus line 70) are formed by using the chromium layer. The pad 92 is exposed through a contact hole formed by patterning with at least one material selected from the gate insulating layer (not shown) and the passivation layer 55 which include SiNx, SiOx or BCB. The pad 92 is connected to a terminal 93 formed by patterning the ITO layer for connecting the output of the driving IC with a TAB. The contact hole for connecting the pad 92 with the terminal 93 is formed by patterning the passivation layer 55 using the etching gas which includes SF6/O2 gas or CF4/O2 gas.
When the contact holes which expose the drain electrode 72 and the pad 92 are formed, as shown in FIGS. 2 and 3, the surface of the chromium layer reacts with the etching gas including SF6/O2 gas or CF4/O2 gas so that a thin insulating layer 75 is formed on the surface of the chromium layer.
The thin insulating layer 75 substantially increases the contact resistivity with the ITO layer, the pixel electrode 80 and the terminal 93. The increased contact resistivity causes distorted electrical characteristics and inferior performance and image quality of the LCD.
There are two reasons why the thin insulating layer 75 is formed on the chromium layer. First, when the insulating layer (gate insulating layer or passivation layer) includes an organic material such as a BCB, the organic material diffuses the chromium layer so that the thin insulating layer 75 is formed. Second, when the surface of the chromium layer is exposed to the etching gas which includes SF6/O2 gas or CF4O2 gas, the thin insulating layer 75 is formed by reacting with the etching gas having the chromium. The detailed mechanism for reacting is certainly not yet revealed. However, based on experience, it has been determined that the contact resistivity of the chromium surface increases when the exposing time that the chromium is exposed to the etching gas is longer as shown in FIG. 4. Rc is the contact resistivity of the chromium surface and T is the exposing time that the chromium surface is exposed to the etching gas.
To overcome the problems described above, preferred embodiments of the present invention provide an LCD and a method of manufacturing an LCD in which an increase in contact resistivity of a metal layer is prevented. More specifically, the preferred embodiments of the present invention prevent the formation of a thin insulating layer on the metal layer which is connected to another conductive material when a contact hole is formed by patterning an insulating layer which covers the metal layer. Preferred embodiments of the present invention also provide an LCD manufacturing method for maintaining the contact resistivity of a metal layer so that the contact resistivity of the metal layer is not changed or affected by an etching gas which is used for patterning an insulating layer disposed on the metal layer.
To solve the above-mentioned problems in the conventional LCD and the method for manufacturing thereof and to achieve the advantages described in the preceding paragraph, a preferred embodiment of the present invention provides an LCD including a metal layer including Mo, W or Ta having a first region and a second region wherein a portion of the thickness of the second region of the metal layer has been removed so that the second layer has a reduced thickness portion and a portion of a thickness of an insulating layer including SiNx, SiOx or BCB which covers the first region of the metal layer is removed so that the insulating layer also has a reduced thickness portion.
According to a specific preferred embodiment, an LCD may include a metal layer which has a first region and a second region having a reduced thickness portion formed by removing greater than or equal to 100 xc3x85 in thickness of the metal layer, and an insulating layer which covers the first region of the metal layer and a conductive layer which contacts the second region of the metal layer. An additional metal layer can be preferably formed under the metal layer in order to further reduce the resistivity of the metal layer.
According to another preferred embodiment of the present invention, a method of manufacturing an LCD includes the steps of forming a metal layer which includes at least one material that is selected from Mo, W and Ta on a substrate, depositing an insulating layer on the metal layer, patterning the insulating layer to expose some portions of the metal layer and removing some thickness of the exposed metal layer.
According to one preferred embodiment of the present invention, a thickness of the exposed metal layer is preferably about 100 xc3x85. Also, the step of removing the exposed metal layer includes etching the metal layer using etching gas which includes SF6/O2 gas or CF4/O2 gas which is used for patterning the insulating layer.